Title:
TDMA通信装置
Document Type and Number:
Japanese Patent JP4486483
Kind Code:
B2
Abstract:
A CPU of a TDMA communications apparatus examines whether a slot to be allocated for a next transmission is a first slot (S1). If the slot to be allocated is the first slot, the CPU examines whether there are any slots already allocated by other stations within a Selection Interval SI in a frame in which the next transmission of own station is to be allocated referring to a slot map in a memory and finds out a free slot within Selection Interval SI (S11). Then, the CPU allocates the free slot as a next transmit slot of the own station and sets the slot number of the free slot as the slot number of the next transmit slot (S12). Then, the CPU examines whether a slot adjacent to the next transmit slot of the own station is allocated to any of the other stations (S13). If either of the slots adjacent to the next transmit slot of the own station is already allocated to another station, the CPU examines a time-out value set by that station for the adjacent slot (S15) and sets an initial time-out value differing from the time-out value set by the other station for the adjacent slot (S16).
Inventors:
Yasushi Hiraoka
Application Number:
JP2004342860A
Publication Date:
June 23, 2010
Filing Date:
November 26, 2004
Export Citation:
Assignee:
FURUNO ELECTRIC COMPANY,LIMITED
International Classes:
H04J3/16; H04W28/26; H04W72/04; H04W74/04
Domestic Patent References:
| JP2004266770A | ||||
| JP2005501466A |
Attorney, Agent or Firm:
Hisao Komori