Title:
TERNARY INPUT DISCRIMINATION CIRCUIT
Document Type and Number:
Japanese Patent JP3461914
Kind Code:
B2
Abstract:
PURPOSE: To provide a ternary input discrimination circuit capable of discriminating the three kinds of input states without the need of a third fixed potential in the input potential of an external terminal.
CONSTITUTION: This ternary input discrimination circuit for discriminating the potential Vi inputted to a first external terminal as one of the prescribed three kinds of the potentials and outputting logic X and Y corresponding to the discriminated potential Vi is provided with a first conductive FET 7 whose source is connected to a first fixed potential Vcc, gate is connected to a second fixed potential Vss and drain is connected to the first external terminal 1, a second conductive FET 8 whose source is connected to the second fixed potential Vss, gate is connected to the first fixed potential Vcc and drain is connected to the first external termini 1, a first discrimination circuit 2 for discriminating the potential Vi inputted to the first external terminal 1 as either first fixed potential Vcc or second fixed potential Vss and second discrimination circuits 3-6 for discriminating the floating state of the first external terminal 1.
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Inventors:
Osamu Kano
Application Number:
JP14790694A
Publication Date:
October 27, 2003
Filing Date:
June 29, 1994
Export Citation:
Assignee:
Renesas lsi design Co., Ltd.
Mitsubishi Electric Corporation
Mitsubishi Electric Corporation
International Classes:
G01R19/165; H03K5/08; H03K19/20; H03M5/16; (IPC1-7): H03K19/20; G01R19/165
Domestic Patent References:
| JP58202628A | ||||
| JP628072A | ||||
| JP614324A | ||||
| JP60119133A | ||||
| JP5191271A | ||||
| JP5203681A | ||||
| JP471001A |
Attorney, Agent or Firm:
Kaneo Miyata (1 person outside)
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