Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
TEST CIRCUIT FOR CLOCK GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP2006333119
Kind Code:
A
Abstract:

To obtain a test circuit for a clock generating circuit that can perform sampling accurately equivalent to modulation cycles to shorten a measurement period and conduct an accurate function test of down-spread control as one modulating function of a spectrum spread clock generator (SSCG) by accurately testing a center frequency.

A comparator 21 converts an analog modulated wave signal Sm from a modulated wave generating circuit 16 into a digital signal Sd and outputs it, a counter 22 counts cycles of a clock signal So outputted from the clock generating circuit according to the digital signal Sd, and a comparing circuit 25 compares the count value with a specification of the center frequency of the clock signal So set in a specification memory 24.


Inventors:
WATABE YUJI
Application Number:
JP2005154310A
Publication Date:
December 07, 2006
Filing Date:
May 26, 2005
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
RICOH KK
International Classes:
G01R31/28; H03K5/19; G06F1/04; H01L21/822; H01L27/04; H03K4/06; H03L7/095; H03M1/34; H04L7/033
Domestic Patent References:
JPS63187949A1988-08-03
JP2002305446A2002-10-18
JP2004207846A2004-07-22
Attorney, Agent or Firm:
Masahiro Ishino



 
Previous Patent: VIDEO TELEPHONE SYSTEM

Next Patent: IMAGE SENSING MODULE