Title:
TEST CIRCUIT FOR SEMICONDUCTOR DEVICE AND TEST METHOD USING THIS TEST CIRCUIT
Document Type and Number:
Japanese Patent JP3540247
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To resolve a deficiency of external terminals for a test.
SOLUTION: For testing a functional block included in a semiconductor device, a test selection signal 118 is fed to a selector circuit 120 to select a test output signal 116, and an output control signal 122 is fed to an output buffer circuit 126. The output is set to high impedance while a test clock signal 12 is kept at a high level, and the test output signal 116 outputted from the selector circuit 120 is outputted to an external terminal 8 while the test clock signal 12 is kept at a low level. A test input signal 112 is received through the external terminal 8 while the test clock signal 12 is kept at a high level, the test output signal 116 is acquired from the external terminal 8 when the low level of the test clock signal 12 is finished, and it is collated with an expected value to judge the presence or absence of an abnormality. Since the external terminal 8 is concurrently used for inputting and outputting the test signal, a deficiency of external terminals can be solved.
Inventors:
Toshiaki Umejima
Application Number:
JP2000142659A
Publication Date:
July 07, 2004
Filing Date:
May 16, 2000
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
G01R31/28; G01R31/3185; G01R31/317; (IPC1-7): G01R31/28; G01R31/317; G01R31/3185
Domestic Patent References:
| JP222866A | ||||
| JP1090362A | ||||
| JP1123663A | ||||
| JP11352194A |
Attorney, Agent or Firm:
Shigeru Noda
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