Title:
TEST CIRCUIT FOR SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3652846
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a wafer burn-in test circuit in which a stress can be applied through bit line stress as well as word line stress and a screening can be performed surely as compared with a conventional one.
SOLUTION: The wafer burn-in test circuit for semiconductor memory employing a sub-word line driver is provided with a switch section SW for feeding a different voltage to the power supply line VSS C, T of each sub-word line driver SWD. A ground power supply VSS is fed commonly to all power supply lines during normal operation whereas the ground power supply VSS and a stress power supply STRESS are fed alternately to the power supply line VSS C of sub-word line driver for true cell and the power supply line VSS T of sub-word line driver for complementary cell during test operation.
Inventors:
Zhao Hidehito
Event
Event
Application Number:
JP25851297A
Publication Date:
May 25, 2005
Filing Date:
September 24, 1997
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G01R31/26; G01R31/28; G11C7/00; G11C11/401; G11C11/407; G11C29/00; G11C29/02; G11C29/06; G11C29/50; H01L21/66; H01L21/8242; H01L27/108; (IPC1-7): G11C29/00
Domestic Patent References:
| JP8055497A | ||||
| JP4000756A | ||||
| JP8227600A | ||||
| JP4225277A | ||||
| JP5342859A |
Attorney, Agent or Firm:
Yasunori Otsuka
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura