PURPOSE: To switch a test mode and a normal mode without adding any test pin by constituting a mode switching means by using only an existent clear terminal and a clock terminal.

CONSTITUTION: When a CLK input is held at an earth potential in a period wherein the negative of CLR input is at the earth potential, D flip-flop 5 is reset and the S input of an R-S latch 4 falls to the earth potential; and then the Q output of the R-S latch 4 is held at the earth potential until the -CLR input varies from a source potential to the earth potential again. The above- mentioned mode is the normal mode and in this mode, the circuit operates as a 12-bit counter. In the test mode, on the other hand, the Q output of the R-S latch 4 is held at the source potential after the negative of CLR input varies from the earth potential to the source potential. When the Q output of the R-S latch 4 is at the source potential, a 4-bit counter 1 performs counting operation simultaneously. Then when the R1 input of the R-S latch 4 falls to the source potential, the Q output of the R-S latch 4 falls to the earth potential and the circuit shown in a figure operates as the normal 12-bit counter.