PURPOSE: To facilitate the generation of test pattern by separating a second FF clock input node from other FF clock nodes in a sequence circuit thereby enhancing the observability and controllability of failure.

CONSTITUTION: In a switch circuit 521, nodes 520, 509 are normally connected and FFs 504, 505 function as in-phase switches for passing signal among blocks. At the time of failure test, the nodes 520, 509 are separated from each other and set with values, respectively, at terminals 519, 516 independently from the outside. In other words, the clock input node of the FF 505 can be controlled separately from the clock nodes of other FF 504 and counter 510 in a sequence circuit at the time of failure test. Since observability and controllability can be enhanced when a decision is made whether the data output, i.e., the node 503, of an FF 506 is failed or not, a test pattern for sequence circuit can be generated easily.