To achieve a built-in memory test method permitting to shorten a test time of built-in DRAM and a bus interface unit and a command decoder used therefor.

In a built-in memory test method, test patterns of DRAM 11 are classified into basic patterns having a common sequence of a memory test command; a control signal containing a basic pattern selection signal for selecting one of the basic patterns is impressed on BIU 13 of DUT 1 from a memory tester 2; and a memory test command based on the basic pattern selection signal is generated with an internal clock cycle generated by a clock generation circuit 14 by multiplying an external clock in a command sequencer 15 in BIU 13.