PURPOSE: To prevent a test mode setting signal from being misinputted and to secure the normal use of the microcomputer by masking an output-stage logic gate according to the specific inhibition pattern of a data signal supplied to an input-stage data pattern decision circuit.
CONSTITUTION: A data pattern decision circuit 1 receives data signals B, C, and D of a specific pattern and turns ON a transistor(TR) 4. A NAND circuit 8 outputs a test mode setting signal A of 'L' level for changing the operation of the microcomputer (not shown in figure) from the normal mode to the test mode when the TR 4 is turned ON. A flip-flop circuit 10 receives the inhibition pattern of the data signal which is the rise of a 1st data signal B and latches the signal of 'L' level, thereby masking the output of the NAND circuit 8. Consequently, the test mode setting signal is prevented from being misinputted and the normal use of the microcomputer can be secured.
| JPH0611486 | [Name of device] Reset state detection circuit |
| JPH02168335 | DATA PROCESSING SYSTEM |
| WO/1996/042045 | OUTPUTTING FORMATTED DEBUG INFORMATION FROM A NETWORK DEVICE |
NAKAIMUKOU MASAYUKI
SEKI MICHIO
