PURPOSE: To form a test pattern having an excellent testing efficiency without waiting the formation of a logic integrated circuit and to test by using it.

CONSTITUTION: A test, in which input patterns are sequentially supplied to a logic integrated circuit and whether the output pattern taken out from the circuit coincides with an expected value pattern or not is judged, is conducted. When mismatch is judged, the testing of the circuit is stopped, and the circuit of next equal type is tested. Before the circuit is formed, the fault occurrence degree of the disconnection or the short-circuit of a signal line is estimated according to wiring conditions obtained from wiring design data, the lines are aligned in the order of estimated fault occurrence degrees, a test pattern for detecting the fault of the line is formed, and used in the descending order of the degree. The estimated fault occurrence degree is so decided that the more the times of crossing a power source supply line is, the longer the wiring length is, the more the number of times of replacing a wiring layer, and the higher the wiring density is, the higher the degree becomes.