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Patent Searching and Data


Title:
TEST PATTERN GENERATING CIRCUIT OF LSI TESTING DEVICE
Document Type and Number:
Japanese Patent JPS5992367
Kind Code:
A
Abstract:

PURPOSE: To reduce the memory capacity of a pattern memory greatly by sorting test patterns and storing as serial data, and specifying the start address of a pattern for every pin of an LSI and taking a test.

CONSTITUTION: The pattern memory 4 is stored with all test patterns while all the test patterns are divided to specific length and the same patterns are unified. The start addresses of patterns which are divided and stored in the pattern memory 4 corresponding to respective input pins are registered in a pattern base address file 5. A bit counter 7 specifies the depth of the patterns and an adder 8 adds a base address from the pattern base address file 5 to a counted value from a bit counter 7 to access the pattern memory 4. The output of the pattern memory is set as data on all input pins by a shift register and latch 9 to generate a pattern.


Inventors:
KAMEDA YASUYOSHI
Application Number:
JP20292282A
Publication Date:
May 28, 1984
Filing Date:
November 19, 1982
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
G01R31/3183; G01R31/319; G01R31/28; G06F11/263; (IPC1-7): G01R31/28; H01L21/66
Attorney, Agent or Firm:
Takehiko Suzue