To make it possible to test all cells of a memory.

This test pattern generator is provided with an address generator 1 which has plural pairs of storing units arranged at least corresponding to plural measuring parts of a device to be measured and each of which has a 1st storing part 21 and a 2nd storing part 22 for storing maximum values of the line addresses and column addresses of the corresponding measuring parts, and a 3rd- and a 4th storing parts 23, 24 for storing X/Y addresses of the row column addresses of the corresponding measuring parts, a selection means 5 for selecting a pair of storing units from the storing units based on a selection signal, and address calculation means 7, 6 for calculating the addresses of testing points of the measuring parts corresponding to the selected storing units of the device to be tested based on the values on the selected units and a control signal; sending these addresses to the corresponding measuring parts of the device to be measured; also sending them to the selected storing units; and replacing the stored addresses therewith.