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Patent Searching and Data


Title:
TEST SYSTEM OF MEMORY IC
Document Type and Number:
Japanese Patent JPS60145599
Kind Code:
A
Abstract:

PURPOSE: To allow high accurate collation by a manual test system and ensure of information on fluctuation width of measurement by discriminating and displaying reading-out check results in accordance with degree of satisfaction with a reading-out cycle.

CONSTITUTION: In accordance with an address of a program from an address register through a skew correction circuit a high speed IC is read out, checked by program data and a comparator, and "fail" and "pass" data are outputted and supplied to a fail and a pass FF51 and FF52, respectively. Checked results by these FF51 and FF52 are logically executed, and the following three types of display are carried out; not satisfied with all reading-out cycles, satisfied with only some reading-out cycles and satisfied with all reading-out cycles. In accordance with these displays manual collation of a skew correction circuit by "SHMOOPLOT" can be carried out at a high accurate level, information on measuring fluctuation width of a test system itself can be secured and a test of a high speed IC can be carried out properly.


Inventors:
NAKAMURA TOMOHARU
Application Number:
JP15184A
Publication Date:
August 01, 1985
Filing Date:
January 04, 1984
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G01R31/28; G01R31/317; G11C29/04; G11C29/00; G11C29/44; (IPC1-7): G01R31/28; G11C29/00
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)