Title:
TESTER AND TESTING METHOD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3130838
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent the delivery of product from being delayed by finding out the cause of failure when failures occur frequently in an electric characteristic test of a semiconductor device on a wafer.
SOLUTION: The tester 100 conducting electric characteristic test of a semiconductor device on a wafer stores the address at a position where the semiconductor device is tested along with the test data in a storing section 112, totalizes the numbers of acceptable and rejectable products for each row on the X an Y axes, calulates the ratio of the number between acceptable and rejectable products, and extracts a row having a ratio being the closest to a predetermined value. Furthermore, a row having the largest total value of the numbers of acceptable and rejectable products is selected and a probing unit 121 is controlled to collects data in one-and-one correspondence between electric characteristics and the diffusion element characteristics for a selected row. According to the method, a data most effective for failure analysis can be sampled automatically and the cause of failure is found out early resulting in the reduction of man-hour required for failure analysis.
Inventors:
Masaru Konno
Application Number:
JP24258697A
Publication Date:
January 31, 2001
Filing Date:
September 08, 1997
Export Citation:
Assignee:
Yamagata NEC Corporation
International Classes:
H01L21/66; G01R31/28; (IPC1-7): H01L21/66; G01R31/28
Domestic Patent References:
| JP7240445A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)