Title:
TESTING DEVICE AND METHOD FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS59125636
Kind Code:
A
Abstract:
PURPOSE:To improve the workability of an integrated circuit testing device by performing a selecting operation on the basis of information of a memory independently at the sorter from a characteristic measuring unit. CONSTITUTION:Chips of wafers which are placed on a stage of a wafer prober 1 are connected to an automatic measuring unit 2 through a probe card and a ring insert, several tens to several hundreds of testing items are measured for an integrated circuit formed on the wafer, and the tested data are memorized in a memory 9 such as floppy disk or the like through a control circuit 8. A marker operation is performed through a control circuit 11 while monitoring the address or the test data of a material to be texted by a monitor unit 12 such as a cathode ray tube via a floppy disk which stores the data in the memory 10 separately from the testing steps of the wafer, and a mark is imprinted on an improper article of the chip to be tested by a marking unit 13.
Inventors:
MUTOU MITSURU
OKADA KATSUHIKO
OKADA KATSUHIKO
Application Number:
JP22867482A
Publication Date:
July 20, 1984
Filing Date:
December 28, 1982
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/66; (IPC1-7): H01L21/66
Domestic Patent References:
| JPS5587452A | 1980-07-02 |
Attorney, Agent or Firm:
Motoaki Hisagi