Title:
半導体装置の試験方法
Document Type and Number:
Japanese Patent JP7427996
Kind Code:
B2
Abstract:
A method for testing a semiconductor chip that has a pn junction constituting a parasitic diode therein includes: causing probe terminals to be in contact with front surface electrodes of the semiconductor chip; obtaining a temperature of the semiconductor chip by measuring electrical characteristics of the parasitic diode through at least one of the front surface electrodes and a back surface electrode and by referring to prescribed temperature characteristics of the parasitic diode; if the obtained temperature is not within a prescribed tolerance from the predetermined target temperature, heating up the semiconductor chip by applying voltage between one or more of the front surface electrodes and the back surface electrode; and once the obtained temperature increases and reaches the predetermined target temperature within the prescribed tolerance, testing electrical characteristics of the semiconductor chip through the front surface electrodes and the back surface electrode.
Inventors:
Mitsuru Yoshida
Application Number:
JP2020022881A
Publication Date:
February 06, 2024
Filing Date:
February 13, 2020
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
G01R31/26; H01L21/66
Domestic Patent References:
| JP2006138711A | ||||
| JP2008281466A | ||||
| JP8101250A | ||||
| JP53145479A |
Attorney, Agent or Firm:
Akinori Sakai