Title:
薄膜トランジスタ表示板及びその製造方法
Document Type and Number:
Japanese Patent JP4732722
Kind Code:
B2
Abstract:
A thin film transistor array panel is provided, which includes a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing a first portion of the semiconductor layer and having edges that coincide with edges of the source and the drain electrodes; and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.
Inventors:
Park Uku
White standard
Lee
Choi Yong
Basis
All phases
White standard
Lee
Choi Yong
Basis
All phases
Application Number:
JP2004239167A
Publication Date:
July 27, 2011
Filing Date:
August 19, 2004
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G02F1/1339; G02F1/1368; G02F1/1343; G02F1/136; G09F9/00; G09F9/30; H01L21/00; H01L21/3205; H01L21/3213; H01L21/336; H01L21/77; H01L21/84; H01L23/52; H01L29/417; H01L29/786; H01L31/036
Domestic Patent References:
| JP2001051297A | ||||
| JP62042127A | ||||
| JP1091468A | ||||
| JP2001230321A | ||||
| JP7094753A | ||||
| JP10240150A | ||||
| JP62229231A | ||||
| JP2000206571A | ||||
| JP2002055362A | ||||
| JP2002353465A | ||||
| JP2005078087A |
Foreign References:
| US20050030440 |
Attorney, Agent or Firm:
Yamashita
Yukio Ono
Tomoko Inazumi
Yukio Ono
Tomoko Inazumi