THIN FILM TRANSISTOR

Japanese Patent JPS63204769

A

PURPOSE: To lessen an OFF current in a polycrystal silicon thin film transistor by preparing a region having an impurity concentration that is lower than those of source and drain electrodes between a polycrystalline silicon layer right below a gate electrode and either of source and drain electrodes.

CONSTITUTION: Regions 5 having a low impurity concentration are formed by causing both sides of a polycrystal silicon 2 to have a prescribed width in its silicon film 2 with a gate electrode 4 as a mask. When a transistor is in a state of OFF, that is, when a negative gate voltage is impressed in the case of an N-channel transistor and when a positive gate voltage is impressed in the case of P-channel transistor, an electric field due to impressed gate and drain electrodes is dispersed in the regions 5 having the low impurity concentration. As a result, the electric field intensity of a drain junction part becomes weaker and carriers moving through a trap in a gain boundary located in the vicinity of the drain junction decrease. Then even though the gate and drain voltages are impressed, no current leakage increases.

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TANAKA KEIJI
ARAI HITOSHI
KODA SHIGETO

JP3577487A

August 24, 1988

February 20, 1987

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NIPPON TELEGRAPH & TELEPHONE

H01L27/12; H01L21/336; H01L29/78; H01L29/786; (IPC1-7): H01L27/12; H01L29/78

JPS58105574A	1983-06-23
JPS58142566A	1983-08-24
JPS57192063A	1982-11-26
JPS59150477A	1984-08-28

Masaki Yamakawa

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