Title:
THREE-DIMENSIONAL FAULT ANALYSIS METHOD FOR SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JP2715289
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To inspect in short time a fault occurred in the metallic wiring layers of a die in a wafer whose process is completed by removing a protection film in a part where the fault part is contained, etching an insulating film between the metallic wiring layers and observing the exposed duplex metallic wirings with a scanning electron microscope.
SOLUTION: The first and second metallic wirings 2a and 2b, the protection film formed on them and an insulating layer between the first and second metallic wirings 2a and 2b are provided. A photosensitive film 3 is applied to the whole face of the protection film except for the prescribed part X containing the fault part in the semiconductor element of such duplex wiring structure. Vinyl 4 is applied to the upper part of the photosensitive film 3 and the side part of the wafer. The exposed protection film on the second metallic wiring 2b is removed and the insulating film between the exposed second metallic wiring layer 2b and the first metallic wiring layer 2a is etched and removed. The duplex metallic wirings 2a and 2b exposed by the etching of the insulating film are observed by controlling an inclination angle and a rotary angle with the scanning electron microscope.
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Inventors:
Kuchong-fe
Application Number:
JP20924496A
Publication Date:
February 18, 1998
Filing Date:
July 19, 1996
Export Citation:
Assignee:
Hyundai Electronics Industry Co., Ltd.
International Classes:
G01N1/32; G01N23/225; H01L21/302; H01L21/3065; H01L21/66; G01N1/28; (IPC1-7): H01L21/66; G01N1/28; G01N1/32; G01N23/225; H01L21/3065
Domestic Patent References:
| JP54118473A | ||||
| JP6326076A |
Attorney, Agent or Firm:
Eiichi Saito