PURPOSE: To reduce the power consumption considerably by adding a transistor(TR) receiving a circuit voltage lower than a high voltage to an intermediate voltage TR circuit and halving the amplitude of an intermediate voltage control signal pulse for a period when an intermediate voltage is outputted at an output terminal.

CONSTITUTION: The 1st P-channel TR gate G1 inputs a high voltage control signal SH to an intermediate voltage TR control circuit 2 in place of an intermediate signal SA and the 2nd P-channel TR QP2 whose drain is connected in common to a node D, whose source receives an internal circuit voltage VC and whose gate G2 receives the 2nd logic input signal S2 is added. A pulse amplitude of the control signal SM is 11V in total (from -7V to 4V), which is nearly a half the pulse amplitude of a conventional control signal Sm (21V) and the pulse current flowing to the gate of the TR QM is halved. As a result, the power consumption of nearly 40% is reduced as a whole.