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Title:
THRESHOLD VALUE CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH10209825
Kind Code:
A
Abstract:

To prevent the generation of the deviation of a threshold level, and to identify a non-signal by outputting a level held higher than a non-signal level only by a forced offset value at the time of inputting no signal, and outputting the voltage-division value of signal amplitude as a threshold level when the input signal level is more than a prescribed value.

A peak detecting circuit 10 with a dead zone outputs a level almost equal to a non-signal level at the time of inputting no signal, and when the level of the input signal is more than a prescribed value, the circuit 10 outputs a 1 side output level lower only by level shift amounts equal to VOF×[(R1+R0)/R0]. In this case, the VOF indicates a forced offset value, and the R0 and R1 indicate resistance values. A voltage dividing circuit operate voltage division at R1:R0 to 1 side and 0 side output levels, and a level shift circuit 12 outputs a level held higher than the non-signal level only by the forced offset value VOF at the time of inputting no signal, and outputs the voltage-division value at the R1:R0 of signal amplitude as a threshold level when the level of the input signal is more than a prescribed value.


Inventors:
IDE SATOSHI
OKUMURA YASUYUKI
Application Number:
JP985197A
Publication Date:
August 07, 1998
Filing Date:
January 23, 1997
Export Citation:
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Assignee:
FUJITSU LTD
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G01R19/04; H03K5/08; (IPC1-7): H03K5/08
Attorney, Agent or Firm:
Teiichi



 
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