To obtain a steep equalizing characteristic and satisfactory phase characteristic, to make an equalizer with high performance small in size and to enable reduction of cost for a system as a whole by cyclically and repeatedly using an FIR filter by way of a register arranged in the FIR filter for processing frequency domain equalization.

A receiving signal inputted from a network via a line transformer 7 is executed AGC, extra-band noise removal, sampling and A-D conversion or the like by an analog front end(AFE) 4 through the receiver of a driver/ receiver 5, and reception data of the result is written in the register which is disposed in AFE 4. A frequency domain equalizer 3 reads a reception signal written in the register via a common bus and temporarily stores the result of equalizing processing execution in a buffer register 8 by the FIR filter 6 which is arranged inside the equalizer 3. Thus, the FIR filter 6 is used cyclicaly and repeatedly by way of the buffer register 8.