To reduce the scale of the hardware while keeping high compatibility with an existing device in the case of applying a bus configuration of an existing time division multiplexer to a small capacity time division multiplexer.

A data memory 13 and a peripheral circuit of the data memory 13 are used in common in terms of parallel data and serial data by conducting input output processing of parallel data of a high rate data exclusive parallel data bus 1 for 64kb/s or over, input output processing of serial data for a serial data bus 2 exclusive for low rate data less than 64kb/s and data inter-conversion processing between parallel data and serial data through timewise serial block divisions for frames so as to save the amount of the hardware.