PURPOSE: To generate a delay time at fail safe, by summing a voltage signal outputted fail safe with a pulse signal outputted by the operation of a shift register.

CONSTITUTION: When an input signal P1 is stopped, since a signal detection circuit CT3 has a time delay longer than that decided at a time element set circuit CT1, even if a pulse signal P2 of the circuit CT1 is stopped, a voltage signal P6 of a signal detection circuit CT2 is kept outputted. An output signal P7 of a summing circuit CT3 is the same as the voltage signal P6. If an open- wire failure takes place, since a voltage value of the signal P6 of the CT2 is zero when the P1 is stopped, the output signal P7 is stopped and a fail-out failure is avoided.