Title:
TIME-OUT DETECTOR FOR COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JP3449495
Kind Code:
B2
Abstract:
PURPOSE: To record the number of time-out events within a prescribed period.
CONSTITUTION: Letters 'I' and 'T' show the start and end events respectively, and the value of a counter and the value of a register that varies by the state bits and the lapse of time are shown in each row of the timing diagram. In regard to an A-counter ('A'), this 'A' is increased by 1 against the start event where an I-bit is equal to zero and also 'A' is reduced by 1 against the end event where a T-bit is equal to zero. As a result, the value 2 is held at a time t4 and at the termination of a 1st pre-scaler period 'A'. This is due to the presence of three start events and an end event. As the I-bit is kept at zero in the same period of times t0 to t4, a B-counter ('B') is set at zero.
Inventors:
Bijoan lean cress
Application Number:
JP13896993A
Publication Date:
September 22, 2003
Filing Date:
May 18, 1993
Export Citation:
Assignee:
Sun Microsystems, Inc.
International Classes:
G06F11/00; H03K21/00; G06F11/30; (IPC1-7): H03K21/00; G06F11/30
Domestic Patent References:
| JP51120640A | ||||
| JP60211550A | ||||
| JP61286949A | ||||
| JP3164966A | ||||
| JP217548A | ||||
| JP1261740A |
Attorney, Agent or Firm:
Masaki Yamakawa
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