Title:
TIME SLOT ALLOCATION SYSTEM FOR TIME DIVISION MULTIPLEX DEVICE
Document Type and Number:
Japanese Patent JP2944490
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce delay time by passing through a time switching circuit by performing bypassing only on a time division multiplex transmission bus or on a time division multiplex reception bus without replacing a time slot.
SOLUTION: Reception data from the outgoing line B-1 of a relay line B are outputted to a TS on the TDM transmission bus E specified from a line interface circuit 2. At the time, at the same timing, the line interface circuit 3 fetches multiplex data from the TDM transmission bus E directly without passing through the time switching circuit 4 and outputs them to the incoming line C-2 of the relay line C. Oppositely, the reception data from the outgoing line C-1 of the relay line C are outputted to the TS on the TDM reception bus F specified from the line interface circuit 3, and at the same timing, the line interface circuit 2 fetches the multiplex data from the TDM reception bus F directly without passing through the time switching circuit 4 and sends them out to the incoming line B-2 of the relay line B.
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Inventors:
FUNAE HIDEAKI
UNNO YOSHINORI
UNNO YOSHINORI
Application Number:
JP30737895A
Publication Date:
September 06, 1999
Filing Date:
November 27, 1995
Export Citation:
Assignee:
SHIZUOKA NIPPON DENKI KK
NIPPON DENKI KK
NIPPON DENKI KK
International Classes:
H04J3/08; H04J3/00; H04J3/06; (IPC1-7): H04J3/00; H04J3/06; H04J3/08
Domestic Patent References:
| JP318140A | ||||
| JP1256243A | ||||
| JP746209A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)