Title:
並列性及びオンチップ・メモリを介した時間、空間及びエネルギー効率のよいニューラル推論
Document Type and Number:
Japanese Patent JP7220007
Kind Code:
B2
Abstract:
Neural inference chips and cores adapted to provide time, space, and energy efficient neural inference via parallelism and on-chip memory are provided. In various embodiments, the neural inference chips comprise: a plurality of neural cores interconnected by an on-chip network; a first on-chip memory for storing a neural network model, the first on-chip memory being connected to each of the plurality of cores by the on-chip network; a second on-chip memory for storing input and output data, the second on-chip memory being connected to each of the plurality of cores by the on-chip network.
Inventors:
Moda, Damendra
Arthur, John, Vernon
Sawada Jun
Ether, Stephen, Kyle
Apaswamy, Latinakumar
Taba, Brian, Saishaw
Cassidy, Andrew, Stephen
Datta, Parab
Flickner, Myron
Penner, Heart Moot
Clamo, Jennifer
Arthur, John, Vernon
Sawada Jun
Ether, Stephen, Kyle
Apaswamy, Latinakumar
Taba, Brian, Saishaw
Cassidy, Andrew, Stephen
Datta, Parab
Flickner, Myron
Penner, Heart Moot
Clamo, Jennifer
Application Number:
JP2020551391A
Publication Date:
February 09, 2023
Filing Date:
March 28, 2019
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
G06N3/063
Foreign References:
| US9710265 | ||||
| US20160321537 |
Other References:
Giacomo Indiveri, et al.,Memory and Information Processing in Neuromorphic Systems,Proceedings of the IEEE,IEEE,2015年07月15日,Vol. 103, No. 8,Pages 1379-1397,,E-ISSN: 1558-2256
Attorney, Agent or Firm:
Tadashi Taneichi
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