Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
TIMER CIRCUIT
Document Type and Number:
Japanese Patent JPS5848527
Kind Code:
A
Abstract:

PURPOSE: To accurately and easily set time, by assembling two stages of inverters having a suitable ratio between the 1st capacitor and the inverter input terminal and increasing the voltage of the 1st capacitor.

CONSTITUTION: A potential change of a capaitor CL is received at an offset circuit 20 consisting of two stages of inverters comprising transistors Q8∼Q11. Then, taking around 1V of the threshold voltage of an output inverter and a linear region of discharge characteristic of a charge pump up to about 2V into consideration, the timer set time accuracy can be increased by using this region only. Thus, the inverting amplification of the inverter is applied, the offset amplifier consisting of the two stages of the inverters is constituted without losing the logic and the ratio of the inverters is set to a suitable value, allowing to easily correct the deviation from the threshold value of the output inverter.


Inventors:
KOBAYASHI SATORU
Application Number:
JP14740081A
Publication Date:
March 22, 1983
Filing Date:
September 18, 1981
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C11/407; H03K17/28; H03K17/284; (IPC1-7): G11C11/34
Attorney, Agent or Firm:
Uchihara Shin



 
Previous Patent: 遊技用システム

Next Patent: SWITCH CIRCUIT