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Title:
TIMER DEVICE
Document Type and Number:
Japanese Patent JPH04122132
Kind Code:
A
Abstract:

PURPOSE: To avoid non-execution of interrupt processing when the capacity of a central processing unit of a base station is exceeded and no task is generated or the central processing unit is destroyed till an interrupt reply is returned and a task is executed by giving an interrupt request to the central processing unit of the base station when timeout processing is not terminated within the specified time.

CONSTITUTION: Let an initial setting value of a counter circuit 11 be, e.g. 3, then a count is decremented by 1 to be 2 by a initial clock signal CLKa and further decremented by 1 to be 1 by a succeeding clock signal CLKb, and an interrupt request circuit 13 outputs an interrupt request (d). When timeout processing is not terminated within a preset time such as 1sec, an interrupt request (e) is set again by a clock signal CLKc. In this case, when a CPU 21 returns an interrupt acknowledge IACK, since the CPU 21 sets the counter circuit 11 to 0, then the operation is stopped. Thus, even in the case of a deficient capacity of a storage device in a base station equipment or destruction of the central processing unit from the return of the interrupt acknowledge till the execution of a task, interrupt processing is implemented.


Inventors:
KATAOKA RIYOUKO
Application Number:
JP24317090A
Publication Date:
April 22, 1992
Filing Date:
September 13, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
G04G15/00; H04B7/26; (IPC1-7): G04G15/00; H04B7/26
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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