PURPOSE: To obtain a timer interruption processing system of less overhead by providing a register or a private counter chip to count the number of times of clock interruption.
CONSTITUTION: If a timer interruption (irg) occurs and is synchronized with the clock from a CPU 5-1, the interruption is validated and a timer counter 5-2 is updated. When the value of the timer counter 5-2 is wanted, it is looked up from the CPU 5-1 by the address and is changed to a correct value and is obtained from the counter 5-2 through a decoder 5-3 by a converter 5-4. The decoder 5-3 resets the counter 5-2 after acquiring data. A delay function 5-5 is used to measure the timing so that the CPU 5-1 does not perform the following instruction processing until data is obtained from the counter 5-2. The value of the timer counter 5-2 obtained in this manner is used to execute the processing related to time-up in the same manner as the use of a register.
YOKOHATA SHIZUO
MAEDA TAKAO
