PURPOSE: To prevent control of a timing clock in an erroneous phase and to recover a stable timing clock by completely masking pulse recognition of an erroneous comparator output resulting from defective bits.

CONSTITUTION: Outputs 2, 3 of a comparator 21 receiving reception signals RD-, RD+ are respectively inputted to mask pulse generating sections 22, 24 to generate mask pulses M+, M-, which are inputted to AND gates 28, 29. Moreover, outputs 2, 3 are inputted respectively to inputs +IN, -IN of a 25% pulse identification and pulse recognition section 27, an oscillator 26 applies a high speed sampling clock to a CLK terminal of the recognition section 27. The recognition section 27 outputs the result of recognition to outputs 6, 7 and a pulse to be excluded due to defective bits in the outputs 6, 7 is excluded by gates 28, 29 to prevent the pulse from entering a violation detection circuit 31. Thus, the stable timing clock is recovered.