PURPOSE: To recover a stable timing clock by masking the detection of violation due to the same polarity pulse within 2 time slots of a reception signal.

CONSTITUTION: Bipolar violation appearing in a reception signal is detected in the step i. Violation caused continuously within 2 time slots (one time slot is equivalent to the pulse width of a frame bit) is excluded in the bipolar violation to be detected in the step ii. The violation not excluded in the step ii is regarded to be a true frame bit in the step iii, a prescribed delay is applied to a generated timing to set the phase of a timing clock to obtain a reference phase. Thus, the control of the timing clock in an erroneous phase is prevented and stable timing clock recovery is realized.