PURPOSE: To cope with the increase of the transmission data speed by changing the pulse width of a differential pulse and adjusting the latch timing of an input signal to fractionate the extent of delay of the clock phase.

CONSTITUTION: A delay differential circuit 32 is provided with a multi-stage gate circuit 32A, and the delay time is varied by setting of a selector 34, and exclusive OR is operated between the signal obtained by variably delaying the input signal and the input signal to output the differential pulse having the variable width. A filter means 40 which takes this differential pulse as the input and permits only the signal of a marrow band with a clock frequency as the center to pass through and a shaping means 60 which shapes the waveform of the output of the filter means 40 to extract the clock component are provided. The pulse width of the differential pulse is changed to adjust the latch timing of the input signal. Consequently, the relative phase difference between the input signal and the clock is adjusted with a half precision of the change of the extent of delay in the delay differential circuit 32.