PURPOSE: To make circuit size compact by connecting an absolute value means for generating the absolute value signal of a signal, a subtracting means for generating a difference signal between the absolute value signal and a signal obtained by delaying the absolute value signal by a half period and an accumulating means for accumulating the difference signal to constitute a phase detecting circuit.

CONSTITUTION: In the phase detecting circuit 11, a switch SW1 samples an input signal at the timing of a clock signal having twice the clock rate of a receiving signal, the absolute value circuit 1 finds out the absolute value of the sampled input, directly sends the absolute value to one input terminal of the subtractor 3 and sends a signal obtained by delaying the absolute signal only by a half clock period of the input signal through a delayer 2 to the other input terminal of the subtractor 3. A switch SW2 samples difference signals sent from the subtractor 3 in every other clock period of the input signal and an adder 4 adds a signal obtained by multiplying its own sending signal by a constant (a) slightly smaller than '1' through a multiplexer 5 and delaying the multiplied signal only by one clock period of the input signal through a delay 6 to its own sending signal and outputs the added signal. Thus, the circuit size can be compacted.