PURPOSE: To execute a high speed operation and to improve delay quantity resolution by supervising the outputs of respective flip flop stages by means of a logical circuit, and generating a timing clock signal when prescribed combination is detected.
CONSTITUTION: Four T-FF1, 2, 3 and 4 are T-type flip flops with load enable functions, and they constitute a down counter (frequency-deviding circuit) in cascade-connection. When a load enable signal 17 is inputted to an LE terminal from host CPU, the signal is enabled and an initial phase set point is set by a D-terminal from a register for initial phase adjustment 10. The logical circuit 25 is synchronized with the clock signal CLK, it inputs Q outputs 6-9 of T-FF1-4 in respective stages and outputs an output signal 26 when a count value consisting of respective Q outputs 6-9 agrees with an instruction value shown by a control signal 27 from CPU.
SUZUKI MASAO
HAYASHI TOSHIO
