Title:
TIMING RECOVERY CIRCUIT
Document Type and Number:
Japanese Patent JP3787790
Kind Code:
B2
Abstract:
PURPOSE: To extend a frequency error range to be traced by controlling accurately a phase of sampling at A/D conversion with respect to the timing recovery circuit for a digital transmission reception circuit.
CONSTITUTION: In a digital reception circuit comprising an A/D converter 1 sampling a received signal and converting the sampled signal into a digital signal, an impulse response estimate section 3 estimating an impulse response of the digital signal to output a pre-cursor as timing information, and a timing recovery circuit 4 generating sampling phase control information to the A/D converter 1 depending on the timing information, the timing recovery circuit 4 is made up of a loop filter 37 eliminating a high frequency component of the impulse response estimate section 3, an accumulator 40 accumulating outputs of the loop filter 37, and a comparator section 41 identifying the accumulated value of the accumulator 40 with a prescribed threshold level to output sampling phase control information and subtracting the accumulated value by the accumulator 40 by the threshold level.
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Inventors:
Yutaka Awata
Nobukazu Koizumi
Otomo Captain
Mitsuo Kadoishi
Nobukazu Koizumi
Otomo Captain
Mitsuo Kadoishi
Application Number:
JP5428194A
Publication Date:
June 21, 2006
Filing Date:
March 25, 1994
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03M1/12; H04L25/03; H03H21/00; H03L7/06; H04B3/06; H04J3/06; H04L7/02; H04L7/00; (IPC1-7): H04L25/03; H03H21/00; H03L7/06; H03M1/12; H04B3/06; H04L7/02
Domestic Patent References:
| JP5183590A | ||||
| JP575390A | ||||
| JP4157836A | ||||
| JP440029A | ||||
| JP29243A | ||||
| JP29244A | ||||
| JP479509A |
Attorney, Agent or Firm:
Manabe Kiyoshi
Shoji Kashiwaya
Koichi Watanabe
Toshiro Ito
Shoji Kashiwaya
Koichi Watanabe
Toshiro Ito