Title:
TIMING SIGNAL GENERATOR
Document Type and Number:
Japanese Patent JPS6354876
Kind Code:
A
Abstract:
PURPOSE:To freely set a generation time or a generation cycle by providing a count means for counting a prescribed repeating signal, a memory means for storing timing information, a data changing means for changing the timing information of the memory means, a reading control means and a timing signal generating means. CONSTITUTION:A selector 32 is set so as to make access to a RAM33 by a CPU17 and the respective data bits of the RAM 33 are set to prescribed values by the CPU17 through a bidirectional bus driver 34 throughout all address areas. Then, when the selector 32 is set to a counter 35 side, the reading operation of the RAM33 is started on the way of the counting of the counter 35, thereafter when as HS signal is initially effective (low level), the phases of clocks phi1, phi2 are registered and then, the data set to the RAM33 is sequentially read from an address '0'. Thereby, an arbitrary timing signal according to the bit set to the RAM33 by the CPU17 is outputted from a flip flop 36.
Inventors:
NAGASHIMA SUNAO
Application Number:
JP19935186A
Publication Date:
March 09, 1988
Filing Date:
August 26, 1986
Export Citation:
Assignee:
CANON KK
International Classes:
H04N1/19; G06T1/00; H04N1/04; H04N3/14; (IPC1-7): G06F15/64; H04N1/04; H04N3/15
Attorney, Agent or Firm:
Marushima Giichi
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