Title:
TIMING SIGNAL REPRODUCING CIRCUIT AND DIGITAL VIDEO SIGNAL PROCESSOR IN DATA TRANSMISSION SYSTEM
Document Type and Number:
Japanese Patent JP3498333
Kind Code:
B2
Abstract:
PURPOSE: To provide a digital video signal processor capable of stably decoding reproducing data even when a transmission rate by variable speed reproduction in a VTR is changed.
CONSTITUTION: A digital VTR quantizes reproducing signals detected through a reproducing head 2, an amplifier 4 and a rotating transformer 6 in an A/D converter 10, quantized data are digitally equalized in a digital equalizer 20 and equalized signals are decoded in a viterbi decoder 14. A phase difference computing element 26 generates plural phase difference signals corresponding to the data transmission rate from the equalized signals, selects the optimum phase difference signal based on state signals from the viterbi decoder 14, drives a VCO 28 by using the selected phase difference signal and generates synchronization clocks from the VCO 28. The clocks become the operation clocks of the A/D converter 10, the digital equalizer 20 and the viterbi decoder 14.
Inventors:
Kaoru Ushiroda
Application Number:
JP26897993A
Publication Date:
February 16, 2004
Filing Date:
October 27, 1993
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H04N5/783; G11B20/14; H03L7/06; H03M5/02; H03M13/23; H04N5/92; H04N19/00; H04N19/59; H04N19/65; H04N19/82; H04N19/85; H04N19/88; H04N19/89; (IPC1-7): H04N5/92; G11B20/14; H03L7/06; H03M5/02; H04N5/783; H04N7/24
Attorney, Agent or Firm:
Takahisa Sato