TIMING SYSTEM REDUCED IN SKEWNESS FOR WRITE-IN CIRCUIT USED FOR MEMORY CIRCUIT - ユナイテッド・メモリーズ・インコーポレーテッド

Title:

TIMING SYSTEM REDUCED IN SKEWNESS FOR WRITE-IN CIRCUIT USED FOR MEMORY CIRCUIT

Document Type and Number:

Japanese Patent JP3492321

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To reduce timing skewness at writing in a memory circuit.
SOLUTION: In the write-in timing system reduced in skewness, a signal on a write-in data line for a memory circuit and a signal on a write-in column selecting line are clocked at an edge which is opposite to a clock signal. Consequently, sensitivity with respect to timing at write-in is relaxed. It is preferable that duty cycle of a clock be approximately 50%, and further it is most preferable that duty cycle be within 5% of that.

Inventors:

Kim carver hardy

Application Number:

JP2001012952A

Publication Date:

February 03, 2004

Filing Date:

January 22, 2001

Export Citation:

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Assignee:

ユナイテッド・メモリーズ・インコーポレーテッド
ソニー株式会社

International Classes:

G11C11/413; G11C11/407; G11C11/409; G11C11/417; (IPC1-7): G11C11/413; G11C11/407; G11C11/417

Domestic Patent References:

JP1196790A
JP2146188A
JP10106264A

Attorney, Agent or Firm:

Makoto Hagiwara

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