Title:
【発明の名称】アダプティブフィルタ修正係数演算回路
Document Type and Number:
Japanese Patent JP2885041
Kind Code:
B2
Abstract:
An arithmetic circuit for adaptive equalizer of Least Mean Square (LMS) algorithm. Includes a real operation part computing a first product between a real part signal of a data sequence and a product of a real part signal of an error sequence and a step coefficient, and computing a second product between an imaginary part signal of the data sequence and a product of an imaginary part signal of the error sequence and a step coefficient. Either of the first and second products is negative. The real operation part further computes a real part of an adaptation coefficient from the first and second products. An imaginary operation part computes a third product between the imaginary part signal of the data sequence and a product of the real part signal of the error sequence and the step coefficient, and computes a fourth product between the real part signal of the data sequence and a product of the imaginary part signal of the error sequence and the step coefficient, so as to obtain an imaginary part of an adaptation coefficient from the third and fourth products.
Inventors:
SHIOKAWA TOSHIMICHI
Application Number:
JP33363893A
Publication Date:
April 19, 1999
Filing Date:
December 27, 1993
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H03H17/02; G06F17/00; H03H21/00; H04L25/03; (IPC1-7): H03H21/00
Domestic Patent References:
| JP62245335A | ||||
| JP613283A | ||||
| JP567172A | ||||
| JP6156823B2 | ||||
| JP605033B2 |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)