Title:
【発明の名称】半導体ウェーハーの拡大光学検査による自動選別器/精査器
Document Type and Number:
Japanese Patent JP2001505299
Kind Code:
A
Abstract:
A method and apparatus for visually inspecting and sorting semiconductor wafers and the individual microcircuits or chips thereon. The preferred embodiment employs a scanner to obtain a virtual reality image of the wafer and all chips are identified and sorted by applying high-speed image processing routines. The resulting wafer map provides unique image controlled chip coordinates making the chips identifiable even after the chips are diced apart. The wafer may contain different kinds of chips in irregular patterns. A gross-defect, visual inspection sorts out defective chips based on image completeness maximizing the yield and throughput. All inspections and identifications are performed on the virtual wafer or chip images scanned into a computer memory with full physical wafer correlation but without having to manipulate the wafer. The inspection time is, therefore, largely free due to overlapping it by regular transport operations.
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Inventors:
Fred Rixen Tea Roland
Chapman Robert El
Chapman Robert El
Application Number:
JP50532998A
Publication Date:
April 17, 2001
Filing Date:
July 07, 1997
Export Citation:
Assignee:
Boker, jay., kent
International Classes:
G01N21/88; G01N21/956; G01R31/28; G01B11/30; G01R31/311; G06T1/00; H01L21/66; G01R31/01; (IPC1-7): G01N21/956; G01B11/30; G06T7/00; H01L21/66
Attorney, Agent or Firm:
Minoru Nakamura (6 outside)