PURPOSE: To increase the opportunities of reading and writing VRAMs by a CPU and to reduce the delay of a moving picture processing in a device for performing the interlace display of a CRT provided with the VRAMs of even-numbered and odd-numbered banks composed of DRAMs.

CONSTITUTION: During the display operation of one of the VRAMs 2-0 and 2-1 by the interlace display, an area specified by the same Y address signal. *RAS as the other VRAM is refreshed and the operation cycle of the CPU 1 required for refreshing is omitted. A control circuit 4 inputs addresses *RAS and *CAS for VRAM data display from the CPU 1 and imparts the addresses *RASO and *CASO and *RAS1 and *CAS1 respectively to the VRAMs 2-0 and 2-1. At the time, *RAS0=*RAS1=*RAS, *CAS0=*CAS and *CAS1=H are defined in the case of an even-numbered field display and *RAS 1=*RAS0=*RAS, *CAS1=*CAS and *CAS0=H are defined in the case of odd-numbered field display.