Title:
【発明の名称】背景雑音発生装置
Document Type and Number:
Japanese Patent JP2762941
Kind Code:
B2
Abstract:
An object of the invention is to provide a background noise generating circuit having a small circuit scale and a small power consumption and capable of setting an arbitrary gain for the background noise. For each frame clock, a circuit (6, 5) generates a gain setting code signal S5 in synchronism with a data clock, and a random generator 21 generates a random number S21 in synchronism with a frame clock FCK. For a period of each frame, a logic gate 22 generates an exclusive-OR between the gain setting code signal S5 and the random number S21, the exclusive-OR constituting a background noise signal S9, which is supplied to a signal processing circuit 7 through a selection circuit 4 during a background noise period. Th gain setting code signal S5 may be determined by detecting the level of a received signal during a received signal input period just before the background noise period, and the gain setting code signal S5 thus determined is held during the background noise period and continues to be supplied to the logic gate.
Inventors:
NAKAGAWA MASASHI
Application Number:
JP30194394A
Publication Date:
June 11, 1998
Filing Date:
December 06, 1994
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H03K3/84; H04B1/04; H04B14/06; H04L12/70; H04N5/00; (IPC1-7): H04L12/56; H03K3/84; H04B14/06
Domestic Patent References:
| JP3226145A | ||||
| JP5235874A | ||||
| JP6125273A | ||||
| JP53459A | ||||
| JP5599824A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)