RANDOM ACCESS MEMORY MODULE HAVING INPUT BUFFER

Title:

RANDOM ACCESS MEMORY MODULE HAVING INPUT BUFFER

Document Type and Number:

Japanese Patent JPS607679

Kind Code:

A

Abstract:

PURPOSE: To attain rapid transmission by incorporating input buffer gates in respective random access memories (RAMs) and driving the plural RAMs through the input buffer gates.

CONSTITUTION: An RAM module 21, RAMs 31W3n, RAM parts 41W4n, and input buffer gates 51W5n are formed and one RAM part and one input buffer gate are built in each RAM. Data are written/read out in/from RAM parts 41W4n through the input buffer gate 51 built in the RAM31. The input side of the input buffer gate 51 is connected to an input pin 3 and the output side is connected to the respective RAM parts 41W4n. Although the input buffer gates 52W5n of other RAMs 32W3n are not used, these gates 52W5n may be selected in accordance with the mounting array of respective devices of the RAM module 21.

More Like This:

JPS63147246	BANK SWITCHING METHOD FOR BANK MEMORY
JPS60186949	MEMORY BANK SYSTEM
JP3198116	[Title of the Invention] A processing system that supports a block writing function.

Inventors:

SERIZAWA ATSUSHI

Application Number:

JP11557183A

Publication Date:

January 16, 1985

Filing Date:

June 27, 1983

Export Citation:

Click for automatic bibliography generation Help

Assignee:

FUJITSU LTD

International Classes:

G06F12/06; G11C7/00; (IPC1-7): G11C7/00

Attorney, Agent or Firm:

Koshiro Matsuoka

Next Patent: DEVICE FOR FORMING MEMORY MODULE SELECTING SIGNAL