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Patent Searching and Data


Title:
NONVOLATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS589286
Kind Code:
A
Abstract:

PURPOSE: To reduce quantity of writing of information and facilitate finding of a defective memory when testing, by making an output of a control potential generating circuit constant even when the power source is changed, and making the potential at the time of normal reading higher than that at the time of testing.

CONSTITUTION: In a control potential generating circuit, signal half turn E/T is made 1 at the time of testing and 0 when normal reading. Reverse signal E/half turn T is reduced to 0 when testing 1 and when reading. Accordingly, a transistor Tr26 is made on state and Tr22 is made off state at the time of testing. Tr22 is made on state, and Tr26 is made off state at the time of normal reading. Consequently, output potential VR becomes the sum of threshold voltage of Tr27 and Tr23 when testing, and attains the sum of threshold voltage of Tr23, Tr24, Tr25 when reading. That is, the potential VR is determined by threshold voltage of Tr23WTr25 and Tr27, Tr23, and does not depends upon the power source Vc. Accordingly, defective memory can be found by this circuit during testing process using low power source voltage, and information can be written at a small quantity of writing.


Inventors:
IWAHASHI HIROSHI
ASANO MASAMICHI
Application Number:
JP10768981A
Publication Date:
January 19, 1983
Filing Date:
July 10, 1981
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G11C11/413; G11C11/34; G11C17/00; G11C29/00; G11C29/12; (IPC1-7): G11C11/34; G11C17/00; G11C29/00
Domestic Patent References:
JPS51140442A1976-12-03
JPS5671898A1981-06-15
Attorney, Agent or Firm:
Takehiko Suzue