PURPOSE: To provide a processor for image codec capable of reducing the capacity of data address storage memory.

CONSTITUTION: Data address sequence (pattern expressing access sequence to data memory 72, 74 by an arithmetic circuit 6 by using a data address) assuming frame DCT is stored in the data address storage memory 2, and when the frame DCT is executed, the data address sequence is used as it is, and when field DCT is executed, the data address sequence is converted at a data address conversion circuit 4, and access to the data memory 72, 74 in which data transfer for field DCT is completed are performed by using converted data address sequence.