Title:
【発明の名称】コマンド入力およびテスト項目設定回路
Document Type and Number:
Japanese Patent JP2975814
Kind Code:
B2
Abstract:
PURPOSE:To upgrade the freedom in the setting of test items. CONSTITUTION:A serial parallel converter, 10 has a holding section to hold eight input signals by seven clocks. On the other hand, a latch pulse generation circuit 20 generates a latch pulse by the eighth pulse. So, in the inputting of a command, eight clocks are inputted to latch a data with a latch circuit 14. In the setting of test items, the setting of the data only is accomplished by inputting seven clocks. In a latch pulse generation circuit 20, the generation of unnecessary latch pulses can be prevented by delaying a specified signal.
More Like This:
| JP2001344998 | SEMICONDUCTOR MEMORY |
| JP4067578 | Testable ICs with analog and digital circuits |
| WO/2009/063359 | GENERAL PURPOSE SERIAL COMMUNICATION USING JTAG INTERFACE |
Inventors:
KAWADA JUNICHI
Application Number:
JP19061993A
Publication Date:
November 10, 1999
Filing Date:
July 30, 1993
Export Citation:
Assignee:
SANYO DENKI KK
International Classes:
G01R31/3185; H01L21/66; H03M9/00; G01R31/28; (IPC1-7): G01R31/3185; G01R31/28
Domestic Patent References:
| JP580128A |
Attorney, Agent or Firm:
Kenji Yoshida (2 outside)