Title:
【発明の名称】コンピュータ入出力キャッシュ・システム
Document Type and Number:
Japanese Patent JP2682789
Kind Code:
B2
Abstract:
Computer architecture and method of control for accomplishing low speed memory to high speed I/O data transfers. An I/O cache is connected between the memory data bus and a system I/O data bus, and is responsive to a storage control unit which manages data transfers over the system I/O bus. The relatively lower speed of the system memory is offset by the larger size of the memory data bus in comparison to the system I/O data bus. The I/O cache is used to prefetch memory data during read cycles, which prefetch operates in concurrence with the transfer of previously prefetched data from the I/O cache to I/O control units on the system I/O data bus. During the writing of data from I/O to system memory, the I/O cache buffers memory access interferences initiated by the processor. The invention permits the use of a conventional and relatively slow main memory in conjunction with a high speed processor and high speed I/O system.
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Inventors:
Ravi Kumar Ali Milli
Warren Edward Moul
David James Sippy
David William Siegel
Warren Edward Moul
David James Sippy
David William Siegel
Application Number:
JP26773193A
Publication Date:
November 26, 1997
Filing Date:
October 01, 1993
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
G06F13/12; G06F12/08; G06F12/0846; G06F12/0862; G06F12/0875; (IPC1-7): G06F13/12
Domestic Patent References:
| JP484253A |
Attorney, Agent or Firm:
Kiyoshi Goda (2 outside)