PURPOSE: To improve the responding properties of a transistor related to a speed, and to increase the operating speed of a logic circuit such as an ECL circuit by applying bias voltage to the transistor through a comparatively large resistor when a P type or N type semiconductor substrate in a bipolar integrated circuit is biassed by fixed potential.
CONSTITUTION: An N- type epitaxial layer 3 is formed through an N+ type buried layer 2 shaped on a P type silicon semiconductor substrate 1, and a P+ type base region 4, an N+ type emitter region 5 and an N+ type collector region 6 are formed on the layer 3 in succession, thus forming an N-P-N type bipolar transistor Q0. A P type diffusion layer 9 is shaped on the epitaxial layer 3, one end of the diffusion layer 9 is connected to supply voltage VEE, and the other end is connected to a P+ region 8 as a lead-in port for substrate voltage. Consequently, reference voltage VEE is applied to the substrate 1 through a resistor R0 consisting of the diffusion layer 9, and the substrate is biassed. Accordingly, parasitic capacitance on the collector side is reduced, and the responding properties of the transistor are improved.
USAMI MITSUO
KOBAYASHI TOORU
HITACHI LTD