Title:
【発明の名称】計数回路
Document Type and Number:
Japanese Patent JP3341421
Kind Code:
B2
Abstract:
PURPOSE:To shorten test pattern length by performing control for up-count and down-count by a clock in a test, and performing the test of all the bit storage elements by two times of input of the clock. CONSTITUTION:The output of an RSFF 73 is set at H and that of an RSFF 74 at L by a reset signal. Also, all the Q output of DFFs 69-72 are set at L by the reset signal. Also, EX-OR gates 66-68 are operated as inverters and a counter is operated as a down counter by setting the output signals of RSFF 73 at H. Then, when a clock signal is inputted for one time. the Q output signal of the DFF 69 goes from L to H, and the Q output of the DFFs 70-72 are varied from L to H sequentially. When the DFF remaining unchanged exists, abnormality can be immediately detected. When no abnormality is found out in the above zero-fault test, hereinafter, the counter is operated as an up counter, and the abnormality can be detected similarly.
Inventors:
Ayumu Kubota
Kunio Nakaguro
Kunio Nakaguro
Application Number:
JP32219493A
Publication Date:
November 05, 2002
Filing Date:
December 21, 1993
Export Citation:
Assignee:
Nissan Motor Co., Ltd
International Classes:
G01R31/3185; G01R31/28; H03K21/40; (IPC1-7): H03K21/40
Domestic Patent References:
| JP63168578A | ||||
| JP396013A |
Attorney, Agent or Firm:
Yoshihiko Izumi